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ah323 2w high linearity 5v 2 - stage amplifier datasheet: rev g 0 6 - 22 - 1 4 - 1 of 17 - disclaimer: subject to change without notice ? 201 4 triqui nt www.triquint.com applications ? base stations / repeaters ? high power amplifiers ? 2g / 3g / 4g wireless infrastructure ? femtocells ? lte / wcdma / cdma 20 pin 5 x 5 mm qfn package func tional block diagram gnd / nc gnd / nc rf out rf out rf out i ref 1 gnd / nc gnd / nc rf in rf in gnd / nc i ref 2 gnd / nc gnd / nc v bias 2 v cc 1 gnd / nc gnd / nc gnd / nc gnd / nc ordering information part no. description ah323 - g 2w 5v 2 - stage amplifier ah323 - pcb2140 2140 mhz evaluation board standard t/r size = 10 00 pieces on a 7 reel pin configuration pin no. label 1 i ref1 4,5 rf in 6 v cc1 11,12,13 rf o ut / v cc 2 16 v bias2 19 i ref 2 2,3,7,8,9,10,14,15, 17,18,20 n/c or gnd backside paddle gnd general description the ah323 is a high dynamic range two - stage driver amplifier in a low - cost surface - mount package. the amplifier is able to achieve high performance across a broad range of frequencies with +50 dbm oip3 and +33 dbm p1db while only consuming 680 ma current. the ingap/gaas hbt integrates two high performance amplifier stages onto a mmic to allow for a more compact system design. the integrated interstage match minimizes performance variation that would otherwise be attributed to external matching component value and placement tolerances. the ah323 is available in a standard lea d - free /green/rohs - compliant 20 pin 5x5mm qf n package. all devices are 100% rf and dc tested. the ah323 is targeted for use as a driver amplifier in wireless infrastructure where high linearity, medium power, and high efficiency are required. this driver amplifier is able to deliver high power whi le maintaining superior aclr performance. the integrated active bias circuitry in the devices enable excellent linearity performance over temperature with little variance. the ah323 is footprint compatible with other triquint 2w devices such as the ah314 for 2.3 - 2.9ghz applications . product features ? 700 - 2700 mhz ? 27.2 db gain at 2140 mhz ? +33 dbm p1db ? high linearity: +50 dbm oip3 ? 24 dbm output power at - 50 dbc wcdma aclr ? integrated inter stage matching ? excellent return loss (>14 db) ? +5v supply voltage ? m ttf > 1000 years
ah323 2w high linearity 5v 2 - stage amplifier datasheet: rev g 0 6 - 22 - 1 4 - 2 of 17 - disclaimer: subject to change without notice ? 201 4 triqui nt www.triquint.com recommended operating conditions parameter min typ max units supply voltage (v cc ) 5.0 6.0 v t case ? 40 +85 c tj for >10 6 hours mttf + 20 0 c electrical specifications are measured at specified test conditions. specifications are not guaranteed over all recommended operating conditions. absolute maximum ratings parameter rating storage temp erature ? 6 5 to 150c rf input power, cw, 50, t=25 c + 18 dbm supply voltage (v cc ) + 8 v device current 1900 ma power dissipation 8 w operation of th is device outside the parameter ranges g iven above may cause permanent damage. electrical specificatio ns test conditions unless otherwise noted: v cc = v pd = +5v , temp= +25c, 50 system. parameter conditions min typ max units operational frequency range 700 2700 mhz test frequency 2140 mhz gain 24.2 27.2 db input return loss 25 db out put return loss 17 db output p1db +32.4 +33.1 dbm output ip3 pout = + 20 dbm/tone, ?f = 1 mhz +44.5 +50 dbm wcdma channel power [1] aclr = - 50 dbc +23.9 db m reference current i ref1 + i ref 2 35 ma quiescent current, icq i cq 1 + i cq 2 600 700 800 ma thermal resistance, jc module (junction to case) 11.7 c/w notes: 1. aclr test set - up: 3gpp wcdma, tm1+64 dpch, +5mhz offset, par = 9.6 db @ 0.01% prob.
ah323 2w high linearity 5v 2 - stage amplifier datasheet: rev g 0 6 - 22 - 1 4 - 3 of 17 - disclaimer: subject to change without notice ? 201 4 triqui nt www.triquint.com reference design 700 - 800 mhz c13 c14 c1 notes: 1. see pc board layout, page 1 5 for more information . 2. vcc1 is connected to vcc2_bias j3 turret via inner layer line. 3. the primary rf microstrip characteristic line impedance is 50 . 4. components shown on the silkscreen but not on the schematic are not used. 5. the edge of c1 is placed at 250 mils from the u1 de vice package (10 @ 750 mhz). 6. the edge of c13 is placed at 50 mils from the edge of u1 device package (2 @ 750 mhz). 7. the edge of c14 is placed at 440 mils from the edge of u1 device package (17.5 @ 750 mhz). 8. zero ohm jumpers may be replaced with copper t races in the target application layout. 9. the locations of c6 and c15 are non - critical. they can be placed closer to the device. c6 can be replaced by 0 ohm jumper. 10. ferrite bead fb1 eliminates bias line resonances between c10 and the parasitic inductance of c11. steward mi0603k300r - 10. 11. all components are of 0603 size unless stated otherwise. 12. c16 is critical for large signal performance. typical performance 700 - 800 mhz test conditions unless otherwise noted: v cc = v pd = +5v, temp= +25c, i cq =700 ma (typ .) parameter conditions units frequency 700 750 800 mhz gain 32.5 32.5 31.2 db input return loss 9.5 16 19 db output return loss 6.6 10 8 db output p1db +32.5 +33 +32.6 dbm oip3 pout = + 2 4 dbm/tone, ?f = 1 mhz +45 +45.7 +45 dbm wcdma channel power [1] aclr = - 50 dbc +22.7 +23.1 +23.6 db m notes: 1. aclr test set - up: 3gpp wcdma, tm1+64 dpch, +5mhz offset, par = 9.6 db @ 0.01% prob. see notes for matching component locations.
ah323 2w high linearity 5v 2 - stage amplifier datasheet: rev g 0 6 - 22 - 1 4 - 4 of 17 - disclaimer: subject to change without notice ? 201 4 triqui nt www.triquint.com performance plots 700 - 800 mhz test conditions unless otherwise noted: v cc = v pd = +5v, temp= +25c, i cq =700 ma (typ.) 28 29 30 31 32 33 700 720 740 760 780 800 gain (db) frequency (mhz) gain vs. frequency temp.=+25 c - 25 - 20 - 15 - 10 - 5 0 700 720 740 760 780 800 return loss (db) frequency (mhz) return loss vs. frequency output rl input rl temp.=+25 c 29 30 31 32 33 34 35 700 720 740 760 780 800 p1db (dbm) frequency (mhz) p1db vs. frequency temp.=+25 c 40 45 50 55 20 21 22 23 24 25 26 oip3 (dbm) pout/tone (dbm) oip3 vs. pout/tone over frequency 800 mhz 750 mhz 700 mhz temp.=+25 c - 65 - 60 - 55 - 50 - 45 - 40 19 20 21 22 23 24 25 aclr (dbc) pout (dbm) aclr vs. pout over frequency 3gpp wcdma, tm1+64dpch, 5mhz offset, 25 c, par = 9.6 db @ 0.1% prob. temp.=+25 c 800 mhz 750 mhz 700 mhz
ah323 2w high linearity 5v 2 - stage amplifier datasheet: rev g 0 6 - 22 - 1 4 - 5 of 17 - disclaimer: subject to change without notice ? 201 4 triqui nt www.triquint.com reference design 800 - 900 mhz c 13 c 14 c 1 notes: 1. see pc board layout, page 1 5 for more information. 2. vcc1 is connected to vcc2_bias j3 turret via inner layer line. 3. the primary rf m icrostrip characteristic line impedance is 50 . 4. components shown on the silkscreen but not on the schematic are not used. 5. the edge of c1 is placed at 225 mils from the edge of u1 device package (10 @ 850 mhz). 6. the edge of c13 is placed at 10 mils from th e edge of u1 device package (0.5 @ 850 mhz). 7. the edge of c14 is placed at 320 mils from the edge of u1 device package (14.5 @ 850 mhz). 8. zero ohm jumpers may be replaced with copper traces in the target application layout. 9. the locations of c6 and c15 are non- critical. they can be placed closer to the device. c6 can be replaced by 0 ohm jumper. 10. ferrite bead fb1 eliminates bias line resonances between c10 and the parasitic inductance of c11. steward mi0603k300r - 10. 11. all components are of 0603 size unless stat ed otherwise. 12. c16 is critical for large signal performance. typical performance 800 - 900 mhz test conditions unless otherwise noted: v cc = v pd = +5v, temp= +25c, i cq =700 ma (typ.) parameter conditions units frequency 800 850 900 mhz gain 31.9 32 31.1 db input return loss 9 14 23 db output return loss 7.7 15 11.7 db output p1db +33 +33.7 +34 dbm oip3 pout = + 24 dbm/tone, ?f = 1 mhz +46 +45.5 +45.3 dbm wcdma channel power [1] aclr = - 50 dbc +23.4 +24.1 +24.1 db m notes: 1. aclr test set - up: 3gpp wcdma, tm1+64 dpch, +5mhz offset, par = 9.6 db @ 0.01% prob. see notes for matching component locations.
ah323 2w high linearity 5v 2 - stage amplifier datasheet: rev g 0 6 - 22 - 1 4 - 6 of 17 - disclaimer: subject to change without notice ? 201 4 triqui nt www.triquint.com performance plots 800 - 900 mhz test conditions u nless otherwise noted: v cc = v pd = +5v, temp= +25c, i cq =700 ma (typ.) 28 29 30 31 32 33 800 820 840 860 880 900 gain (db) frequency (mhz) gain vs. frequency temp.=+25 c - 25 - 20 - 15 - 10 - 5 0 800 820 840 860 880 900 return loss (db) frequency (mhz) return loss vs. frequency temp.=+25 c output rl input rl 31 32 33 34 35 36 800 820 840 860 880 900 p1db (dbm) frequency (mhz) p1db vs. frequency temp.=+25 c 40 45 50 55 20 21 22 23 24 25 26 oip3 (dbm) pout/tone (dbm) oip3 vs. pout/tone over frequency temp.=+25 c 900 mhz 850 mhz 800 mhz - 60 - 55 - 50 - 45 - 40 20 21 22 23 24 25 26 aclr (dbc) pout (dbm) aclr vs. pout over frequency temp.=+25 c 900 mhz 850 mhz 800 mhz 3gpp wcdma, tm1+64dpch, 5mhz offset, 25 c, par = 9.6 db @ 0.1% prob.
ah323 2w high linearity 5v 2 - stage amplifier datasheet: rev g 0 6 - 22 - 1 4 - 7 of 17 - disclaimer: subject to change without notice ? 201 4 triqui nt www.triquint.com reference design 1 800 - 1 900 mhz c 13 c 3 notes: 1. see pc board layout, page 1 5 for more information. 2. vcc1 is connected to vcc2_bias j3 turret via inner layer line. 3. the pr imary rf microstrip characteristic line impedance is 50 . 4. components shown on the silkscreen but not on the schematic are not used. 5. the edge of c2 is placed at 128 mils from the u1 device package (12.5 @ 1850 mhz). 6. the edge of c3 is placed at 70 mils fro m the edge of u1 device package (7 @ 1850 mhz). 7. the edge of c13 is placed at 110 mils from the edge of u1 device package (10.7 @ 1850 mhz). 8. zero ohm jumpers may be replaced with copper traces in the target application layout. 9. the locations of c6 and c15 are non - critical. they can be placed closer to the device. c6 can be replaced by 0 ohm jumper. 10. ferrite bead fb1 eliminates bias line resonances between c10 and the parasitic inductance of c11. steward mi0603k300r - 10. 11. all components are of 0603 size unless stated otherwise. typical performance 1 800 - 1 900 mhz test conditions unless otherwise noted: v cc = v pd = +5v, temp= +25c, i cq =700 ma (typ.) parameter conditions units frequency 1800 1850 1900 mhz gain 28.6 28.8 28.6 db input return loss 13 1 7.6 20.5 db output return loss 10.5 13 14.4 db output p1db +33.2 +33.3 +33.1 dbm oip3 pout = + 24 dbm/tone, ?f = 1 mhz +49 +50 +49 dbm wcdma channel power [1] aclr = - 50 dbc +23.7 +23.9 +23.9 db m notes: 1. aclr test set - up: 3gpp wcdma, tm1+64 dpch, +5mhz offset, par = 9.6 db @ 0.01% prob. see notes for matching component locations.
ah323 2w high linearity 5v 2 - stage amplifier datasheet: rev g 0 6 - 22 - 1 4 - 8 of 17 - disclaimer: subject to change without notice ? 201 4 triqui nt www.triquint.com performance plots 1 800 - 1 900 mhz test conditions unle ss otherwise noted: v cc = v pd = +5v, temp= +25c, i cq =700 ma (typ.) 25 26 27 28 29 30 1800 1820 1840 1860 1880 1900 gain (db) frequency (mhz) gain vs. frequency temp.=+25 c - 25 - 20 - 15 - 10 - 5 0 1800 1820 1840 1860 1880 1900 return loss (db) frequency (mhz) return loss vs. frequency temp.=+25 c output rl input rl 40 45 50 55 60 20 21 22 23 24 25 26 oip3 (dbm) pout/tone (dbm) oip3 vs. pout/tone over frequency temp.=+25 c 1900 mhz 1850 mhz 1800 mhz 40 45 50 55 60 20 21 22 23 24 25 26 oip3 (dbm) pout/tone (dbm) oip3 vs. pout/tone over temperature temp.=+25 c freq = 1850 mhz +85 c +25 c ?40 c 29 30 31 32 33 34 35 1800 1820 1840 1860 1880 1900 p1db (dbm) frequency (mhz) p1db vs. frequency over temperature +85 c +25 c ?40 c - 65 - 60 - 55 - 50 - 45 - 40 20 21 22 23 24 25 26 aclr (dbc) pout (dbm) aclr vs. pout over frequency temp.=+25 c 3gpp wcdma, tm1+64dpch, 5mhz offset, 25 c, par = 9.6 db @ 0.1% prob. 1900 mhz 1850 mhz 1800 mhz - 65 - 60 - 55 - 50 - 45 - 40 20 21 22 23 24 25 26 aclr (dbc) pout (dbm) aclr vs. pout over temperature freq = 1850 mhz +85 c +25 c ?40 c 3gpp wcdma, tm1+64dpch, 5mhz offset, 25 c, par = 9.6 db @ 0.1% prob.
ah323 2w high linearity 5v 2 - stage amplifier datasheet: rev g 0 6 - 22 - 1 4 - 9 of 17 - disclaimer: subject to change without notice ? 201 4 triqui nt www.triquint.com reference design 193 0 - 1 9 9 0 mhz c 13 c 3 notes: 1. see pc board layout, page 1 5 for more information. 2. vcc1 is connected to vcc2_bias j3 turret via inner layer line. 3. the pri mary rf microstrip characteristic line impedance is 50 . 4. components shown on the silkscreen but not on the schematic are not used. 5. the edge of c2 is placed at 128 mils from the u1 device package (13 @ 1960 mhz). 6. the edge of c3 is placed at 70 mils from t he edge of u1 device package (7.3 @ 1960 mhz). 7. the edge of c13 is placed at 100 mils from the edge of u1 device package (10.4 @ 1960 mhz). 8. zero ohm jumpers may be replaced with copper traces in the target application layout. 9. the locations of c6 and c15 a re non - critical. they can be placed closer to the device. c6 can be replaced by 0 ohm jumper. 10. ferrite bead fb1 eliminates bias line resonances between c10 and the parasitic inductance of c11. steward mi0603k300r - 10. 11. all components are of 0603 size unless s tated otherwise. typical performance 1 930 - 1 9 9 0 mhz test conditions unless otherwise noted: v cc = v pd = +5v, temp= +25c, i cq =700 ma (typ.) parameter conditions units frequency 1930 1960 1990 mhz gain 28.9 28.8 28.6 db input return loss 20 24 22 db output return loss 16.5 19.6 20.6 db output p1db +33.2 +33.1 +33.1 dbm oip3 pout = + 24 dbm/tone, ?f = 1 mhz +50.3 +50.3 +50.3 dbm wcdma channel power [1] aclr = - 50 dbc +24 +23.8 +23.8 db m notes: 1. aclr test set - up: 3gpp wcdma, tm1+64 dpch, +5mhz offset, par = 9.6 db @ 0.01% prob. s ee notes for matching component locations.
ah323 2w high linearity 5v 2 - stage amplifier datasheet: rev g 0 6 - 22 - 1 4 - 10 of 17 - disclaimer: subject to change without notice ? 201 4 triqui nt www.triquint.com performance plots 193 0 - 1 9 9 0 mhz test conditions unless otherwise noted: v cc = v pd = +5v, temp= +25c, i cq =700 ma (typ.) 25 26 27 28 29 30 1930 1940 1950 1960 1970 1980 1990 gain (db) frequency (mhz) gain vs. frequency temp.=+25 c - 25 - 20 - 15 - 10 - 5 0 1930 1940 1950 1960 1970 1980 1990 return loss (db) frequency (mhz) return loss vs. frequency temp.=+25 c output rl input rl 29 30 31 32 33 34 35 1930 1940 1950 1960 1970 1980 1990 gain (db) frequency (mhz) p1db vs. frequency temp.=+25 c 45 50 55 60 20 21 22 23 24 25 26 oip3 (dbm) pout/tone (dbm) oip3 vs. pout/tone over frequency temp.=+25 c 1990 mhz 1960 mhz 1930 mhz - 65 - 60 - 55 - 50 - 45 - 40 20 21 22 23 24 25 26 aclr (dbc) pout (dbm) aclr vs. pout over frequency temp.=+25 c 1990 mhz 1960 mhz 1930 mhz 3gpp wcdma, tm1+64dpch, 5mhz offset, 25 c, par = 9.6 db @ 0.1% prob.
ah323 2w high linearity 5v 2 - stage amplifier datasheet: rev g 0 6 - 22 - 1 4 - 11 of 17 - disclaimer: subject to change without notice ? 201 4 triqui nt www.triquint.com ah323 - pcb 2140 evaluation board ( 2110 ? 217 0 mhz) c 13 c 3 notes: 1. see pc board layout, page 1 5 for more information. 2. vcc1 is connected to vcc2_bias j3 turret via inner lay er line. 3. 7khsulpdu5)plfurvwulsfkdudfwhulvwlfolqhlpshgdqfhlv 4. components shown on the silkscreen but not on the schematic are not used. 5. the edge of c2 is placed at 128 mils from the u1 device package (14.5 @ 2140 mhz). 6. the edge of c3 is placed at 80 mils from the edge of u1 device package (9 @ 2140 mhz). 7. the edge of c13 is placed at 70 mils from the edge of u1 device package (8 @ 2140 mhz). 8. zero ohm jumpers may be replaced with copper traces in the target application layout. 9. the locations of c6 and c15 are non - critical. they can be placed closer to the device. c6 can be replaced by 0 ohm jumper. 10. ferrite bead fb1 eliminates bias line resonances between c10 and the parasitic inductance of c11. steward mi0603k300r - 10. 11. all components are of 0603 s ize unless stated otherwise. 12. low cost ceramic sq series capacitors are used for matching. typical performan ce C ah323 - pcb 2140 test conditions unless otherwise noted: v cc = v pd = +5v, temp= +25c, i cq =700 ma (typ.) parameter conditions units frequ ency 2110 2140 2170 mhz gain 27.3 27.2 27 .0 db input return loss 20 25 32 db output return loss 17 16.6 17 db output p1db +33.2 +33.1 +33.1 dbm oip3 pout = + g%pwrqhi 1 mhz +49.7 +50 +50 dbm wcdma channel power [1] aclr = - 50 dbc +24 +23.9 +23.9 db m noise figure 4.2 4.2 4.3 db notes: 1. aclr test set - up: 3gpp wcdma, tm1+64 dpch, +5mhz offset, par = 9.6 db @ 0.01% prob. see notes for matching component locations.
ah323 2w high linearity 5v 2 - stage amplifier datasheet: rev g 0 6 - 22 - 1 4 - 12 of 17 - disclaimer: subject to change without notice ? 201 4 triqui nt www.triquint.com performance plots C ah323 - pcb 2140 test conditions unless otherwise noted: v cc = v pd = +5v, temp= +25c, i cq =700 ma (typ.) 24 25 26 27 28 29 2110 2120 2130 2140 2150 2160 2170 gain (db) frequency (mhz) gain vs. frequency temp.=+25 c - 30 - 25 - 20 - 15 - 10 - 5 0 2110 2120 2130 2140 2150 2160 2170 return loss (db) frequency (mhz) return loss vs. frequency temp.=+25 c output rl input rl 0 1 2 3 4 5 2110 2120 2130 2140 2150 2160 2170 noise figure (db) frequency (mhz) noise figure vs. frequency temp.=+25 c 29 30 31 32 33 34 35 36 2110 2120 2130 2140 2150 2160 2170 p1db (dbm) frequency (mhz) p1db vs. frequency over temperature +85 c +25 c ?40 c 45 47 49 51 53 55 18 19 20 21 22 23 24 25 26 oip3 (dbm) total pout (dbm) oip3 vs. total pout temp.=+25 c 2170 mhz 2140 mhz 2110 mhz 45 47 49 51 53 55 20 21 22 23 24 25 26 oip3 (dbm) total pout (dbm) oip3 vs. total pout freq = 2140 mhz +85 c +25 c - 40 c - 65 - 60 - 55 - 50 - 45 - 40 20 21 22 23 24 25 26 aclr (dbc) pout (dbm) aclr vs. pout over frequency temp.=+25 c 2170 mhz 2140 mhz 2110 mhz 3gpp wcdma, tm1+64dpch, 5mhz offset, 25 c, par = 9.6 db @ 0.1% prob. - 65 - 60 - 55 - 50 - 45 - 40 20 21 22 23 24 25 26 aclr (dbc) pout (dbm) aclr vs. pout over temperature freq = 2140 mhz +85 c +25 c ?40 c 3gpp wcdma, tm1+64dpch, 5mhz offset, 25 c, par = 9.6 db @ 0.1% prob.
ah323 2w high linearity 5v 2 - stage amplifier datasheet: rev g 0 6 - 22 - 1 4 - 13 of 17 - disclaimer: subject to change without notice ? 201 4 triqui nt www.triquint.com reference design 2 5 00 - 2700 mhz c 13 c 3 notes: 1. see pc board layout, page 1 5 for more information. 2. vcc1 is connected to vcc2_bias j3 t urret via inner layer line. 3. the primary rf microstrip characteristic line impedance is 50 . 4. components shown on the silkscreen but not on the schematic are not used. 5. the edge of c2 is placed at 128 mils from the u1 device package (18 @ 2650 mhz). 6. the edge of c3 is placed at 75 mils fr om the edge of u1 device package (10.5 @ 2650 mhz). 7. the edge of c13 is placed as close as possible to the edge of u1 device package. 8. zero ohm jumpers may be replaced with copper traces in the target application layout. 9. the locations of c6 and c15 are non - critical. they can be placed closer to the device. c6 can be replaced by 0 ohm jumper. 10. ferrite bead fb1 eliminates bias line resonances between c10 and the parasitic inductance of c11. steward mi0603k300r - 10. 11. all components are of 0603 size unless stated o therwise. typical performance 2 5 00 - 270 0 mhz test conditions unless otherwise noted: v cc = v pd = +5v, temp= +25c, i cq =700 ma (typ.) parameter conditions units frequency 2500 26 0 0 2700 mhz gain 23.5 23 2 2 db input return loss 9.5 15.5 2 1 db output return loss 9 1 3 1 5 db output p1db +3 2 +33 +3 3 dbm oip3 pout = + 24 dbm/tone, ?f = 1 mhz +4 4 +4 4 . 5 +4 5 dbm wcdma channel power [1] aclr = - 50 dbc +2 2 .5 +23 .3 +23 .5 db m notes: 1. aclr test set - up: 3gpp wcdma, tm1+64 dpch, +5mhz offset, par = 10.2 db @ 0.01% prob. see notes for matching component locations.
ah323 2w high linearity 5v 2 - stage amplifier datasheet: rev g 0 6 - 22 - 1 4 - 14 of 17 - disclaimer: subject to change without notice ? 201 4 triqui nt www.triquint.com performance plots 2 5 00 - 2700 mhz test conditions unless otherwise noted: v cc = v pd = +5v, temp= +25c, i cq =700 ma (typ.) 20 21 22 23 24 25 2500 2550 2600 2650 2700 gain (db) frequency (mhz) gain vs. frequency temp.=+25 c - 30 - 25 - 20 - 15 - 10 - 5 0 2500 2550 2600 2650 2700 return loss (db) frequency (mhz) return loss vs. frequency temp.=+25 c output rl input rl 29 30 31 32 33 34 35 2500 2550 2600 2650 2700 p1db (dbm) frequency (mhz) p1db vs. frequency temp.=+25 c 40 45 50 55 60 20 21 22 23 24 25 26 oip3 (dbm) pout/tone (dbm) oip3 vs. pout/tone temp.=+25 c 2700 mhz 2600 mhz 2500 mhz - 65 - 60 - 55 - 50 - 45 - 40 20 21 22 23 24 25 26 aclr (dbm) pout (dbm) aclr vs. pout over frequency temp.=+25 c 2700 mhz 2600 mhz 2500 mhz 3gpp wcdma, tm1+64dpch, 5mhz offset, 25 c, par = 10.2 db @ 0.1% prob.
ah323 2w high linearity 5v 2 - stage amplifier datasheet: rev g 0 6 - 22 - 1 4 - 15 of 17 - disclaimer: subject to change without notice ? 201 4 triqui nt www.triquint.com evaluation board pcb information triquint pcb 1076269 material and stack - up 1 oz. cu bottom layer nelco n-4000-13 nelco n-4000-13 r =3.9 typ. nelco n-4000-13 1 oz. cu top layer 1 oz. cu inner layer 1 oz. cu inner layer 0.014" 0.014" 0.062" 0.006" finished board thickness pin configuration and description gnd / nc gnd / nc rf out rf out rf out i ref1 gnd / nc gnd / nc rf in rf in gnd / nc i ref2 gnd / nc gnd / nc v bias2 v cc1 gnd / nc gnd / nc gnd / nc gnd / nc pin no. label description 1 i ref1 refer ence current into internal active bias current mirror. current into iref sets device quiescent current for first stage. it can be used as on/off control. iref 1 current is set by providing +5vpd through dropping resistor on evb . 4,5 rf in input, requires match ing for operation. 6 v cc1 supply voltage for first stage amplifier. rf choke is needed. 11,12,13 rf o ut / v cc 2 output , requires match ing for operation. supply voltage for 2 nd stage amplifier. rf choke is needed. 16 v bias2 voltage supply for active bias for second stage. bypass cap is recommended. 19 i ref2 reference current into internal active bias current mirror. current into iref sets device quiescent current for 2 nd stage. it can be used as on/off control. iref 2 current is set by providing +5 vpd through dropping resistor on evb . 2,3,7,8,9,10,14,15,17, 18,20 n/c or gnd no internal connection. this pin can be grounded or n/c on pcb. backside paddle rf / dc gnd rf/dc ground. use recommended via pattern to minimize inductance and thermal resist ance. see pcb mounting pattern .
ah323 2w high linearity 5v 2 - stage amplifier datasheet: rev g 0 6 - 22 - 1 4 - 16 of 17 - disclaimer: subject to change without notice ? 201 4 triqui nt www.triquint.com mechanical information package marking and dimensions marking: part number C ah323g year/week/country code - yyww lot code C a axxxx n otes : 1. all dimensions are in millimeters. angles are in degrees. 2. dimension and tolerance formats conform to asme y14.4m - 1994. 3. the terminal #1 identifier and terminal numbering conform to jesd 95 - 1 spp -012. pcb mounting pattern notes: 1. all dimensions are in millimeters. angles are in degrees. 2. use 1 oz. copper minimum for top and bottom layer metal . 3. a heatsink underneath the area of the pcb for the mounted device is required for proper thermal operation. 4. ground / thermal vias are critical for the proper performance of this device. vias should use a .35mm (#80 / .0135) diameter drill and have a fin al plated thru diameter of .25 mm (.010). 5. add as much copper as possible to inner and outer layers near the part to ensure optimal thermal performance.
ah323 2w high linearity 5v 2 - stage amplifier datasheet: rev g 0 6 - 22 - 1 4 - 17 of 17 - disclaimer: subject to change without notice ? 201 4 triqui nt www.triquint.com product compliance information esd sensitivity ratings caution! esd - sensitive device esd rating: class 1c value: passes 100 0 v to < 20 00 v test: human body model (hbm) standard: jedec standard jesd22 - a114 esd rating: class c3 value: > 1 000 v test: charged device model (cdm) standard: jedec standard jesd22 - c101 solderability compa tible wi th both lead - free (260 c max. reflow temperature) and tin/lead (245 c max. reflow temperature) soldering processes. contact plating: annealed matte tin over copper rohs compliance this part is compliant with eu 2002/95/ec rohs directive (restri ctions on the use of certain hazardous substances in electrical and electronic equipment). this product also has the following attributes: x lead free x halogen free (chlorine, bromine) x antimony free x tbbp - a (c 15 h 12 br 4 0 2 ) free x pfos free x svhc free msl rating msl rating : level 3 test: 260c convection reflow standard: jedec standard ipc/jedec j - std - 020 contact information for the latest specifications, additional product information, worldwide sales and distribution locations, and information about tri quint: web: www.triquint.com tel: +1.503.615.9000 email: info - sales@triquint.com fax: +1.503.615.8902 for technical questions and application information: email: sjcapplications.engineering@triquint.com important notice the information contained herein is believed to be reliable. triquint makes no warranties regarding the information con tained herein. triquint assumes no responsibility or liability whatsoever for any of the information contained herein. triquint assumes no responsibility or liability whatsoever for the use of the information contained herein. the information contained herein is provided "as is, where is" and with all faults, and the entire risk associated with such information is entirely with the user. all information contained herein is subject to change without notice. customers should obtain and verify the latest relevant information before placing orders for triquint products. the information contained herein or any use of such information does not grant, explicitly or implicitly, to any party any patent rights, licenses, or any other intellectual property rights , whether with regard to such information itself or anything described by such information. triquint products are not warranted or authorized for use as critical components in medical, life - saving, or life - sustaining applications, or other applications w here a failure would reasonably be expected to cause severe personal injury or death.

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